The speed performance of an electronic system is often limited by the speed at which either information signals or clock signals or both can be propagated to the various load elements in the system. For example, the system can be (or can be part of) an integrated circuit located on a single silicon chip ("substrate"), and the load elements can be, for example, such elements or devices as inverters, NOR gates, OR gates AND gates, NAND gates, transmission gates ("pass transistors"), flip-flop devices, or tri-state buffers. These logic gates thus constitute "destination logic gates" (or "destination load elements") for the information signals or the clock signals or both the information and the clock signals. The various differences in arrival times of a given signal at different destination gates within the system ("propagation time delays") impose a limitation on the speed performance of the system. These differences in arrival times are caused by different propagation time delays ("temporal dispersion") in the transmission of the propagating signal to the destination load elements.
Within a synchronous system whose timing is controlled by a clock signal (i.e., a periodic, rectangular shaped signal), the timing is ordinarily limited by the delays in the arrivals of the edge of this clock signal at the various destination load elements: the longest such delay in the clock signal determines the so-called "latency time" of the system. The delays in other (e.g., "data") signals are not as critical, since the important feature of these other signals is their sufficient magnitude (and not their sharpness) at the moment of time of arrival of the clock edge. Hence the temporal dispersions of these other signals do not constitute a limiting factor on the operation of the system, owing to the more severe limitation imposed by the temporal dispersion of the (hopefully sharp) edges of the clock signal arriving at different destination gates. As used herein, the term "latency time" refers to the longest time delay of the clock signal to any destination gate in the system.
For example, FIG. 1 shows an exemplary prior-art electronic system including an input buffer B formed by two cascaded inverters. This input buffer B is fed by a clock signal source C that serves as a source of the clock signals. The input buffer B has an output node N0, serving as an input terminal for delivery of the clock signals to an electrical transmission line L0. This electrical transmission line L0 is connected to a total of illustratively thirty-two destination load elements G1, G2,...G31, and G32. These destination load elements will be referred to generically as G for brevity and convenience. The destination load elements G thus control the flow of data in a thirty-two-bit data "bus" controlled by the destination load elements, as will be explained in greater detail below. The load elements G are represented pictorially in FIG. 1 by load inverters G solely for purposes of illustration: any of these load elements G can be any other type of clocked logic gate, clocked buffers, clocked flip-flop devices, or clocked transmission gate. At any rate, since all the destination load elements G are controlled by at least the clock signal supplied by the clock source C, these elements G can be referred to more comprehensively as "clock-signal-controlled destination load elements" G.
As indicated in FIG. 2, an exemplary load element such as G1 can take the form of a clock-controlled ("clocked") logic gate, such as a clocked OR gate. In addition to the clock signal propagating from the electrical transmission line L0 to an input terminal i1 of this load element G1, this OR gate has as inputs a pair of input signals D11 and D21. Thus when either of the input signals D11 or D21 is a digital "1" ("high" level signal), the output of the gate G1 at its output terminal g1 is assuredly also a digital "1" as soon as the clock signal (typically a clock edge) arrives at the input terminal i1 of the destination load element G1. Thus the destination load element G1 is clocked-as are all the other destination load elements G-by the arrival of the clock signal (typically the edge thereof) propagating along the electrical transmission line L0 to their respective clock input terminals.
In one approach of prior art, in order to compensate for signal amplitude losses and signal degradations (losses of original signal wave shape) suffered along the electrical transmission line L0 as the clock signal propagates from the input terminal N0 of the electrical transmission line L0 to the destination load elements G, a repeater r (signal amplifier) is inserted as shown (FIG. 1). These losses and degradations are caused by the resistances and capacitances along the electrical transmission line L0, especially by the input capacitances of the destination load elements G. The electrical transmission line L0 can have a number of cascaded repeaters r or instead can have a number of cascaded drivers that increase in current-drive capability going down the line away from the input terminal N0-as described, for example, in a paper by H. B. Bakoglu et al., published in IEEE Transaction On Electron Devices, Vol. ED-32, pp. 903-909 (May, 1985), especially at p. 906, FIG. 5.
The electrical transmission line L0 (FIG. 1) is typically a "zero'th" metallization level polysilicon wire ("line") having unavoidable distributed parasitic capacitance to the silicon substrate and unavoidable distributed resistance along this electrical transmission line. As compared with all other levels of metallization, zero'th level polysilicon lines are located closest to the underlying silicon substrate. Nevertheless, the parasitic capacitance (to substrate ground) per unit length of zero'th level line is not significantly higher than that of an equally long metallic line located on the first or second or still higher levels of metallization: most of length of the electrical transmission line is located on relatively thick field oxide rather than relatively thin gate oxide. However, the resistance per unit length of zero'th level wire is significantly higher than that of first or higher level metallization, and therefore this resistance contributes to undesirable "RC" time delays along the electrical transmission line L0.
In addition, the input capacitance with which the clock signal is confronted at the input terminal of each of the destination load elements G constitutes another parasitic, and this parasitic contributes further unwanted capacitance faced by the propagating clock signal. For example, in MOS (metal oxide semiconductor) technology, this parasitic input capacitance is the capacitance of the gate electrode of the transistor to which the electrical transmission line L0 is connected.
Because of these parasitic resistances and capacitances, unavoidable "RC" time delays are suffered by clock signal edges propagating from the output node N0 to the various load elements G. The RC time delays depend upon the geometry (topology) of the various paths along the electrical transmission line L0 from the output node N0 of the buffer B to the load elements G. The load elements G that are located in closer proximity to the node N0 receive their clock signal edges from this node N0 earlier than the load elements G that are located more remotely from the node N0. Hence these time delays are different from one another ("temporal dispersion"). The longest such time delay can be relatively very long in case the relevant effective RC for the worst case load element G (i.e., G32) is relatively large. Thus, in a worst case scenario, the system can suffer both from an undesirably long latency time and from an undesirably large signal skew. As used herein, the term "signal skew" refers to the situation in which the propagation time delays for the various loads are different from one another.
Another problem that arises in the system shown in FIG. 1 stems from the fact that a clock signal edge involves a sharp jump, the sharpness of which is undesirably degraded by the time the edge arrives at some of the more remotely located load elements G.
FIG. 3 shows a system illustratively including a 32-bit clocked data bus showing one way in which prior art attempted to mitigate one or more of the foregoing problems: namely, by means of an added electrical transmission line L2 having a lower resistance per unit length than that of the electrical transmission line L0. The added electrical transmission line L2 can be located, for example, either on the zero'th (typically, polysilicon) metallization level or on a second (typically, metallic or metallic-like) metallization level, the second metallization level being separated from a major surface of the substrate by a larger distance than the zero'th. That is to say, neglecting small contributions by gate oxide regions relative to field oxide regions of a zero'th metallization level added electrical transmission line L2 to average distance of separation of this added electrical transmission line L2 from the major surface of the substrate, the average distance of separation d2 of a zero'th metallization level added electrical transmission line L2 from the major surface of the substrate is equal to the average distance of separation d1 of the zero'th metallization level electrical transmission line L0 from the major surface of the substrate. Similarly the average distance of separation d2 of a second metallization level added transmission line L2 from the major surface of the substrate is significantly greater than the average distance of separation d1 of the zero'th metallization level transmission line L0 from the major surface of the substrate. At the same time, the repeater r is omitted, and the electrical-current-drive capability of (e.g., the transistor widths in) the buffer B is increased. The electrical transmission line L2 runs essentially parallel to the electrical transmission line L0.
As further shown in the example illustrated in FIG. 3, an input terminal of illustratively every fourth destination load element (load inverter) G is connected to a proximate node of the added electrical transmission line L2, typically by means of a separate, relatively low resistance connection (electrically "passive strap") denoted by P1, ..., P8.
Because of the straps P1, ..., P8, even without any repeater in the system shown in FIG. 3, propagation time delays are reduced somewhat as compared with the propagation time delays suffered in the system shown in FIG. 1. However, the amount of these delays can still be higher than may be desired owing to the input capacitances of the destination load elements, although signal skew is dramatically reduced as compared to the system shown in FIG. 1. Furthermore, in the system shown in FIG.3, sharp signal edges can still suffer from an undesirable amount of degradation. A passive strapping scheme, similar to that shown in FIG.3, was disclosed in the context of reducing word-line delays in high density RAMs (random access memories) in a paper by Kiyofumi Ochii et al., published in 85 IEEE International Solid-State Circuits Conference, pp. 64-65,306 (February, 1985) at p.64 col. 2.
Therefore it would be desirable to have an electronic system that mitigates one or more of the aforementioned shortcomings of prior art.